Portable electronic devices require higher functionality and capacities in a limited size at a lowest possible cost. This has driven the industry to increase integrations not only on the silicon level but also at the package level, that is, by stacking bare dies onto one package or stacking known good packages together to realize higher functionality and density.
The primary limitation to the stacked dies approach is the low final package yield as it is inevitable that some of the dies in the package may have low yield because of design complexity or processing related issues. If these low yield dies are included in the stacking configuration without pre-testing, the compound yield of the final package which is the product of the individual die test yields can be unacceptably low.
In addition, the need to pre-test or burn-in devices along with other technical requirements such as poor heat dissipation path and possible electromagnetic interference (EMI make the stacked dies less attractive.
U.S. Pat. No. 6,577,013 entitled “Chip Size Semiconductor Packages with Stacked Dies”, issued on Jun. 10, 2003, describes stacking of multiple dies to form a chip-size package. The dies are stacked on one another in such a way that terminal pads of each die are aligned so that through silicon via can pass through the terminal pads and these pads are interconnected through an electrically conductive wire or pin inserted in the vias.
In addition to the common problems associated with bare die stacking, the obvious drawback existed in the prior art is that this vertical connection approach only allows same dies to be stacked in a particular configuration. This because the conductive pin or wire must be inserted in the silicon via that penetrates through the terminal pads of the individual dies in order to provide the connection. In other words, if a different die is placed in the stack, its terminal pads may not be in the specified vertical path to be connected and thus may result in these terminal pads being isolated and not providing the designated functions. Furthermore, as most of the terminal pads on the die surface are relatively small, the effective dimension of the drilled silicon via needs to be sufficiently small to be put within the peripheral of the pad to avoid destroying the pad. The small silicon via hole dictates a thin and fragile pin to be inserted mechanically and this can be a serious problem as it is not practical for volume production due to its low throughput and manufacturing yield.
U.S. Pat. No. 6,908,785 entitled “Multi-Chip Package (MCP) with a Conductive Bar and Method for Manufacturing the Same” issued on Jun. 21, 2005 describes another bare die stacking architecture in which a plurality of pad re-distribution lines are deposited on the die surface in order to relocate the original terminal pads for the vertical connection.
Although this app roach provides a more flexible method in stacking and eases the strict restriction of vertical connection only through the origin a pads, the bare die stacking of this approach still suffers the drawback that vertical stacking has to be carried out within the die boundary. Furthermore, the relocated pads need to be in the area where there is no active circuitry underneath. This is to ensure that through silicon vias do not destroy the circuits and affect chip's proper function. This can not be practically possible unless these areas are designated and reserved in advance.
Integrating silicon density or functionality can be achieved by stacking finished packages to form a multi-package module. In this approach each die is assembled in a respective package first and then integrated together to maximize performance and minimize cost. This approach can provide numerous advantages as compared to stacked die packages.
For instance, before the packages are stacked, each package can be electrically test, and rejected unless it shows satisfactory performance. As a result, the final stacked multi-package module yields are maximized.
More efficient cooling can be provided in stacked packages by inserting a heat spreader between the packages in the stack as well as at the top of the module.
Package level stacking also allows electromagnetic shielding on the RF (radio frequency) dies and minimizes interference with other dies within the module.
However, stacking one package on top of another can be a challenge if the encapsulant that is deposited on the chip completely blocks off the vertical interconnecting channel. As such, in the package-on-package stacking configuration, enabling a z-axis connection to interconnect top and bottom packages is a critical technology from the viewpoints of manufacturability, design flexibility and cost. Many z-interconnect approaches for stacking have been proposed, including peripheral solder ball connection, and flexible substrate folded over the top of the bottom package, and so on.
The use of peripheral solder balls in a package-on-package configuration greatly limits the design flexibility, and results in a low yield and a large size package. The use of a flexible folding substrate in general provides a better design flexibility, but it suffers a less established manufacturing infrastructure for the folding process. Moreover, flexible folding requires a two metal layer flex substrate, which is a more expensive material. Furthermore, the folded flexible substrate approach is restricted to relatively low pin-count applications because of the limitations in routing of the circuitry in two metal layer substrates.
The limitations of the solder ball connection are described in further detail with reference to FIG. 6 and FIG. 7.
FIG. 6 is a diagrammatic cross sectional view of a conventional Ball Grid Array (“BGA”) package. The BGA package 600 comprises a semiconductor chip 610 and an interconnect board 620. The semiconductor chip 610 has a plurality of input/output (I/O) pads 611 disposed at a first surface 610a of the semiconductor chip 610, which is provided with a plurality of integrated circuits (ICs). The interconnect board 620 is bonded to a second surface 610b of the semiconductor chip 610 by means of an adhesive 630, such as a die attach epoxy. The interconnect board 620 has a dielectric substrate 621. A circuit pattern 622 provided with wire bond finger 624 is formed on a first surface of the dielectric substrate 621. Another circuit pattern 623 provided with a plurality of conductive lands 625 is formed on a second surface of the dielectric substrate 621. Each of the circuit patterns 622,623 has a conductive material such as copper, and is connected together by way of plated through via 626. Solder masks 627,628 are patterned over the dielectric substrate 621 and the circuit patterns 622,623 separately with underlying metal exposed at bonding sites for providing electrical connections, for example the wire bond fingers 624 and conductive lands 625 for bonding the wires 640 and solder balls 670 respectively.
The I/O pad 611 of the semiconductor chip 610 is electrically connected to the wire bond finger 624 in the first surface of the interconnect board 620 by means of conductive wires 640. In order to protect the semiconductor chip 610 and the wire 640 from the external environment, the first surface of the interconnect board 620 is encapsulated by a resin encapsulant 650 to facilitate handling operation. After encapsulation, a plurality of solder balls 670 are reflowed to be fused onto conductive lands 625 on the circuit pattern 623 to provide interconnections to the circuit board
FIG. 7 is a diagrammatic sectional view illustrating the structure of an example of a 2-stack package-on-package board 700, in which a z-interconnect between packages in a stacking format is obtained by way of solder balls 775.
In this stacked structure the bottom package is similar to that shown in FIG. 6, which has a plurality of conductive lands on the first surface of the dielectric substrate. These conductive lands are located at the periphery of the package and are not encapsulated by the molding compound. Another package (which is referred to as the “top” package) is stacked on the bottom package and is similar in structure to the bottom package, except that the solder balls in the top package are only arranged at the peripheral of the package.
The z-axis connection in the 2-stacked package-on-package is achieved by reflowing of the solder balls 775 to the conductive lands at the upper surface of the bottom package to effect z-axis interconnection without interfering with the encapsulation of the bottom BGA.
The above mentioned conventional stacked package has some problems in that the distance between the top and bottom packages must be at least the encapsulation height of the bottom package, which is typically in a range between 0.5 mm and 1.5 mm. Accordingly, the solder balls 775 must be of a sufficiently large diameter so that, when reflowed, they make good contact with the bonding pads of the bottom BGA; that is, the diameter of the solder ball 775 must be greater than the bottom package's encapsulation height. A larger ball diameter dictates a larger ball pitch that in turn limits the number of balls that can be fitted within the limited space.
The above mentioned conventional stacked package configuration forces the stacked package to be significantly larger than the dimension of a standard BGA due to the peripheral arrangement of the solder balls. It becomes a problem that it cannot be applied to a variety of miniature electronic appliances, such as memory modules, memory cards, cellular phones, notebooks and PDAs.
U.S. Pat. No. 6,716,038, entitled “Z-axis Connection of Multiple Substrates by Partial Insertion of Bulges of a Pin”, issued on Apr. 6, 2004, describes a three dimensional circuit module using twisted pins to electrically connect multiple, spaced-apart circuit board. An obvious drawback exists in this prior art is that there is no metallurgical connection between the pin and the plated through hole, and the physical contacts are not reliable under various heat treatments during board assembly.
In view of the various development stages and limitations in currently available semiconductor chip assemblies, there is a need for a semiconductor chip assembly that is cost-effective, reliable, and provides a vertical connection with excellent mechanical and electrical properties, and makes advantageous use the particular connection joint technique best suited for a given application.
Hence, the prior arts do not fulfill all users' requests on actual use.